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Integrated Circuit Systems, Inc.
ICS950410
Advance Information
AMD - K8TM System Clock Chip
Recommended Application: AMD K8 System Clock with AMD, VIA or ALI Chipset
Pin Configuration
~*FS0/REF0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 REF1/FS1* GND VDDREF Reset# VDDA GND CPUCLK8T0 CPUCLK8C0 VDDCPU CPUCLK8T1 CPUCLK8C1 GND VDDCPU CPUCLK8T2 CPUCLK8C2 GND Turbo# PD#* 48MHz/FS3** GND AVDD48 24_48MHz/Sel24_48#*
Output Features: VDDHTT * 3 - Differential pair push-pull CPU clocks @ X1 3.3V X2 * 9 - PCICLK (Including 1 free running) @ 3.3V GND * 3 - Selectable PCICLK/HTTCLK @ 3.3V *ModeA/HTTCLK0 * 1 - HTTCLK @ 3.3V *ModeB/PCICLK8/HTTCLK1 * 1 - 48MHz @ 3.3V fixed. PCICLK9/HTTCLK2 * 1 - 24/48MHz @ 3.3V VDDPCI * 2 - REF @ 3.3V, 14.318MHz. GND Features: PCICLK11/HTTCLK3 * Programmable output frequency. *FS2/PCICLK10 * Programmable output divider ratios. PCICLK0 * Programmable output rise/fall time. PCICLK1 * Programmable output skew. GND * Programmable spread percentage for EMI VDDPCI control. PCICLK2 * Watchdog timer technology and RESET# output PCICLK3 to reset system VDDPCI if system malfunctions. GND * Programmable watch dog safe frequency. 2X PCICLK4 * Support I2C Index read/write and block read/ 2X PCICLK5 write operations. 2X PCICLK6 * Uses external 14.318MHz crystal. 2X PCICLK7 * Supports Hyper Transport Technology (HTTCLK).
ICS950410
26 SDATA 25 SCLK
48-SSOP
Functionality
2X
* Internal Pull-Up Resistor
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50
This Output has 2X Default Drive and can be programmaed lower via IIC ~ This Output has 1.5x drive
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0888--04/06/04 ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
ICS950410
Advance Information
Pin Descriptions
PIN # PIN NAME 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 ~*FS0/REF0 VDDHTT X1 X2 GND *ModeA/HTTCLK0 *ModeB/PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 VDDPCI GND PCICLK11/HTTCLK3 *FS2/PCICLK10 PCICLK0 PCICLK1 GND VDDPCI PCICLK2 PCICLK3 VDDPCI GND 2XPCICLK4 2XPCICLK5 2XPCICLK6 2XPCICLK7 SCLK SDATA 24_48MHz/Sel24_48#* AVDD48 GND 48MHz/FS3** PD#* Turbo# GND CPUCLK8C2 CPUCLK8T2 VDDCPU GND CPUCLK8C1 CPUCLK8T1 VDDCPU CPUCLK8C0 CPUCLK8T0 GND VDDA Reset# VDDREF GND REF1/FS1* PIN TYPE I/O PWR IN OUT PWR I/O I/O OUT PWR PWR OUT I/O OUT OUT PWR PWR OUT OUT PWR PWR OUT OUT OUT OUT IN I/O I/O PWR PWR I/O IN IN PWR OUT OUT PWR PWR OUT OUT PWR OUT OUT PWR PWR OUT PWR PWR I/O DESCRIPTION Frequency select latch input pin / 14.318 MHz reference clock. Supply for HTT clocks, nominal 3.3V. Crystal input, Nominally 14.318MHz. Crystal output, Nominally 14.318MHz Ground pin. Mode selection latch input pin / Hyper Transport output. Mode selection latch input pin / PCI clock output / Hyper Transport output. PCI clock output / Hyper Transport output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output / Hyper Transport output. Frequency select latch input pin / 3.3V PCI clock output. PCI clock output. PCI clock output. Ground pin. Power supply for PCI clocks, nominal 3.3V PCI clock output. PCI clock output. Power supply for PCI clocks, nominal 3.3V Ground pin. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. PCI clock output. This output is default @ 2X drive and can be programmed to lower drive via IIC. Clock pin of SMBus circuitry, 5V tolerant. Data pin for SMBus circuitry, 5V tolerant. 24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 = 24MHz. Analog power for 48MHz outputs and fixed PLL core, nominal 3.3V Ground pin. Fixed 48MHz clock output. 3.3V / 'Frequency select latch input pin Asynchronous active low input pin used to power down the device. The internal clocks are disabled and the VCO and the crystal are stopped. Real time input pin to change frequency to a pre-programmed under or over clock entries located in IIC Rom table. Ground pin. Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Ground pin. Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Supply for CPU clocks, 3.3V nominal Complimentary clock of differential 3.3V push-pull K8 pair. True clock of differential 3.3V push-pull K8 pair. Ground pin. 3.3V power for the PLL core. Real time system reset signal for frequency gear ratio change or watchdog timer timeout. This signal is active low. Ref, XTAL power supply, nominal 3.3V Ground pin. 14.318 MHz reference clock / Frequency select latch input pin.
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ 1.5X Drive Strength
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ICS950410
Advance Information
General Description
The ICS950410 is a main system clock solution for desktop designs using the AMD K8 CPU. It provides all necessary clock signals for Clawhammer and Sledgehammer with AMD, VIA or ALI systems. The ICS950410 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). This part incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment.
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum
48MHz 24_48MHz
REF (1:0)
CPU DIVDER
CPUCLKC (2:0) CPUCLKT (2:0)
PD# SDATA SCLK FS (3:0) MODE (A,B) SEL24_48# Turbo# Config. Reg. Control Logic
PCI DIVDER
PCICLK (7:0, 10)
HTT DIVDER
PCICLK(11,9,8)/HTTCLK (3:1)
HTTCLK0
Power Groups
Pin Number VDD 2 9 16,19 29 35,38 43 46
0888--04/06/04
GND 5 10 15,20 27,30,33 34,39 42 47
Description Xtal, POR PCICLK, HTTCLK O/p PCICLK Outputs 48 MHz, Fix Analog CPU Outputs Analog, CPU PLL, MCLK REF, Digital Core
3
ICS950410
Advance Information
Table1: Frequency Selection Table
Bit4 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Bit3 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit2 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit0 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU MHz 100.90 133.90 168.00 202.00 100.20 133.50 166.70 200.40 150.00 180.00 210.00 240.00 270.00 233.33 266.67 300.00 100.00 133.33 166.66 200.00 103.00 137.33 171.66 206.00 154.49 185.38 216.31 247.20 278.10 240.34 274.68 308.97 HTT MHz 67.27 66.95 67.20 67.33 66.80 66.75 66.68 66.80 60.00 60.00 70.00 60.00 67.50 66.67 66.67 75.00 66.67 66.67 66.66 66.67 68.67 68.66 68.66 68.67 61.79 61.79 72.10 61.80 69.53 68.67 68.67 77.24 PCI MHz 33.63 33.48 33.60 33.67 33.40 33.38 33.34 33.40 30.00 30.00 35.00 30.00 33.75 33.33 33.33 37.50 33.33 33.33 33.33 33.33 34.33 34.33 34.33 34.33 30.90 30.90 36.05 30.90 34.76 34.33 34.34 38.62
Mode Functionality Tables
ModeA 0 0 1 1 ModeB 0 1 0 1 Pin7 HTTCLK1 HTTCLK1 PCICLK8 HTTCLK1 Pin8 HTTCLK2 HTTCLK2 PCICLK9 PCICLK9 Pin11 PCICLK11 HTTCLK3 PCICLK11 PCICLK11
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ICS950410
Advance Information
General I2C serial interface information How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) * ICS clock will acknowledge each byte one at a time * Controller (host) sends a Stop bit * * * * * * * *
How to Read:
* * * * * * * * * * * * * * Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host) starT bit T Slave Address D2(H) WR WRite Beginning Byte = N ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
Index Block Read Operation
Controller (Host) T starT bit Slave Address D2(H) WR WRite Beginning Byte = N ACK RT Repeat starT Slave Address D3(H) RD ReaD ACK Data Byte Count = X ACK Beginning Byte N ACK X Byte ICS (Slave/Receiver)
ACK
ACK
Byte N + X - 1 ACK P stoP bit
Byte N + X - 1 N P
0888--04/06/04
Not acknowledge stoP bit
5
ICS950410
Advance Information
I C Table: Frequency Select Register
Byte 0 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name SS_EN SEL24_48MHz FS Source Select FS4 FS3 FS2 FS1 FS0
Control Function Spread Enable Output Select FS Source Select Freq Select Bit 4 Freq Select Bit 3 Freq Select Bit 2 Freq Select Bit 1 Freq Select Bit 0
Type RW RW RW RW RW RW RW RW
0 OFF 48MHz latch
1 ON 24MHz I2C
PWD 1 Latch 0 0 Latch Latch Latch Latch
7 6 5 4 3 2 1 0
See Table1: Frequency Selection Table
I C Table: Output Control Register
Byte 1 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # 1 6 7 8 11 12 13 14
Name CPUCLK8T/C2 HTTCLK0 PCICLK8/HTTCLK1 PCICLK9/HTTCLK2 PCICLK11/HTTCLK3 PCICLK10 PCICLK0 PCICLK1
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Output Control Register
Byte 2 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # 17 18 21 22 23 24 28 31
Name PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 PCICLK7 24_48MHz 48MHz
Control Function Output Control Output Control Output Control Output Control Output Control Output Control Output Control Output Control
Type RW RW RW RW RW RW RW RW
0 Disable Disable Disable Disable Disable Disable Disable Disable
1 Enable Enable Enable Enable Enable Enable Enable Enable
PWD 1 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Output Control Register
Byte 3 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 37,36 41,40 45,48 Pin # Name CPUCLK8T/C_1 CPUCLK8T/C_0 Reserved REF0/REF1 PCI_Str1 PCI_Str0 PCI_Str1 PCI_Str0 Control Function Output Control Output Control Reserved Output Control PCI9,8 Strength Control only PCI11 Strength Control only Type RW RW RW RW RW RW RW RW 0 Disable Disable Disable 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 1 Enable Enable Enable 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive PWD 1 1 1 1 0 1 0 1
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ICS950410
Advance Information
I C Table: Output Control Register
Byte 4 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0 PCIStr1 PCIStr0
Control Function All other PCICLK Strength Control PCICLK (7:6) Strength Control PCICLK (5) Strength Control PCICLK (4) Strength Control
Type RW RW RW RW RW RW RW RW
0 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive 00: 0.5X Drive 01: 1.0X Drive
1 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive 10: 1.5X Drive 11: 2.0X Drive
PWD 0 1 1 1 1 1 1 1
7 6 5 4 3 2 1 0
I C Table: Reserved Register
Byte 5 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Control Function Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
Type RW RW RW RW RW RW RW RW
0 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
PWD X X X X X X X X
7 6 5 4 3 2 1 0
I C Table: Byte Count Register
Byte 6 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0
Control Function
Type RW RW RW RW RW RW RW RW
0
1
PWD 0 0 0 0 0 1 1 0
7 6 5 4 3 2 1 0
Byte Count Programming b(7:0)
Writing to this register will configure how many bytes will be read back, default is 06 = 6 bytes.
I C Table: Byte Count and Vendor ID Register
Byte 7 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name REV_ID3 REV_ID2 REV_ID1 REV_ID0 Vendor_ID3 Vendor_ID2 Vendor_ID1 Vendor_ID0 Control Function Type RW RW RW RW RW RW RW RW 0 1 PWD 0 0 0 0 0 0 0 1
Revision ID
Vendor ID
0888--04/06/04
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ICS950410
Advance Information
I C Table: Skew Control Register
Byte 8 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name PCI/HTTSkw3 PCI/HTTSkw2 PCI/HTTSkw1 PCI/HTTSkw0 PCISkw3 PCISkw2 PCISkw1 PCISkw0
Control Function CPU-PCI/HTT 7 Step Skew Control (ps)
Type RW RW RW RW RW RW RW RW
0 0000:0 0001:N/A 0010:N/A 0011:N/A 0000:0 0001:N/A 0010:N/A 0011:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A 0100:150 0101:N/A 0110:N/A 0111:N/A
1 1000:300 1001:N/A 1010:N/A 1011:N/A 1000:300 1001:N/A 1010:N/A 1011:N/A 1100:450 1101:600 1110:750 1111:900 1100:450 1101:600 1110:750 1111:900
PWD 1 1 0 0 1 1 0 0
7 6 5 4 3 2 1 0
CPU-PCI 7 Step Skew Control (ps)
I C Table: WD Time Control & Async Frequency Selection Register
Byte 9 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
2
Pin # -
Name ASEL AEN REF1 Strength Reserved WDTCtrl WD2 WD1 WD0
Control Function Async Frequency Select AGP/PCI/ Freq Source Select REF1 strength control Reserved Watch Dog Time base Control WD Timer Bit 2 WD Timer Bit 1 WD Timer Bit 0
Type RW RW RW RW RW RW RW RW
0 66MHz FIX PLL 1x 290ms Base
1 75.4MHz CPU PLL 2x 1160ms Base
PWD 0 1 1 1 0 1 1 1
These bits represent X*290ms (or 1.16S) the watchdog timer waits before it goes to alarm mode. Default is 7 X 290ms = 2s.
I C Table: VCO Control Select Bit & WD Timer Control Register
Byte 10 Bit 7 Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name M/NEN WDEN WDStatus WD SF4 WD SF3 WD SF2 WD SF1 WD SF0
Control Function M/N Programming Enable Watchdog Enable WD Alarm Status
Type RW RW R RW RW RW RW RW
0 Disable Disable Normal
1 Enable Enable Alarm
PWD 0 0 0 0 0 0 0 0
6 5 4 3 2 1 0
Watch Dog Safe Freq Programming bits
Writing to these bit will configure the safe frequency as Byte0 bit (4:0).
I C Table: VCO Frequency Control Register
Byte 11 Bit Bit Bit Bit Bit Bit Bit Bit 7 6 5 4 3 2 1 0 Pin # Name N Div8 N Div9 M Div5 M Div4 M Div3 M Div2 M Div1 M Div0 Control Function N Divider Prog bit 8 N Divider Prog bit 9 Type 0 1 PWD X X X X X X X X RW The decimal representation of N Divider in Byte 11 and 12 RW RW The decimal representation of M and N RW Divider in Byte 11 and 12 will configure M Divider Programming RW the VCO frequency. Default at power up = bits (5:0) latch-in or Byte 0 Rom table. RW RW VCO Frequency = 14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2] RW
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ICS950410
Advance Information
I C Table: VCO Frequency Control Register
Byte 12 Bit Bit Bit Bit Bit Bit Bit Bit
2
2
Pin # -
Name N Div7 N Div6 N Div5 N Div4 N Div3 N Div2 N Div1 N Div0
Control Function
Type
0
1
PWD X X X X X X X X
7 6 5 4 3 2 1 0
RW RW The decimal representation of M and N RW Divier in Byte 11 and 12 will configure the VCO frequency. Default at power up = N Divider Programming RW latch-in or Byte 0 Rom table. bit (7:0) RW RW VCO Frequency = 14.318 x [NDiv(8:0)+8] / [MDiv(6:0)+2] RW RW
I C Table: Spread Spectrum Control Register
Byte 13 Bit Bit Bit Bit Bit Bit Bit Bit
2
Pin # -
Name SSP7 SSP6 SSP5 SSP4 SSP3 SSP2 SSP1 SSP0
Control Function
Type RW RW RW RW RW RW RW RW
0
1
PWD X X X X X X X X
7 6 5 4 3 2 1 0
Spread Spectrum Programming b(7:0)
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
I C Table: Spread Spectrum Control Register
Byte 14 Bit 7 Bit 6 Bit Bit Bit Bit Bit Bit 5 4 3 2 1 0 Pin # Name Reserved SSP14 SSP13 SSP12 SSP11 SSP10 SSP9 SSP8 Control Function Reserved Type R RW RW RW RW RW RW RW 0 1 PWD 0 X X X X X X X
Spread Spectrum Programming b(14:8)
These Spread Spectrum bits in Byte 13 and 14 will program the spread pecentage. It is recommended to use ICS Spread % table for spread programming.
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ICS950410
Advance Information
Absolute Maximum Rating
PARAMETER 3.3V Core Supply Voltage 3.3V Logic Input Supply Voltage Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection HBM
1
SYMBOL VDD_A VDD_In Ts Tambient Tcase ESD prot
CONDITIONS -
MIN
TYP
MAX VDD + 0.5V
UNITS V V
Notes 1 1 1 1 1 1
GND - 0.5 -65 0 2000
VDD + 0.5V 150 70 115
C
C C V
Guaranteed by design and characterization, not 100% tested in production.
Electrical Characteristics - Input/Supply/Common Output Parameters
PARAMETER Input High Voltage Input Low Voltage Input High Current SYMBOL VIH VIL IIH IIL1 Input Low Current IIL2 Low Threshold InputHigh Voltage Low Threshold InputLow Voltage Operating Supply Current Operating Current Powerdown Current Input Frequency Pin Inductance Input Capacitance VIH_FS VIL_FS IDD3.3OP IDD3.3OP IDD3.3PD Fi Lpin CIN COUT CINX Clk Stabilization Modulation Frequency Tdrive_PD# Tfall_Pd# Trise_Pd# SMBus Voltage VDD TSTAB Logic Inputs Output pin capacitance X1 & X2 pins From VDD Power-Up or deassertion of PD# to 1st clock Triangular Modulation CPU output enable after PD# de-assertion PD# fall time of PD# rise time of 2.7 CONDITIONS* 3.3 V +/-5% 3.3 V +/-5% VIN = VDD VIN = 0 V; Inputs with no pull-up resistors VIN = 0 V; Inputs with pull-up resistors 3.3 V +/-5% 3.3 V +/-5% Full Active, CL = Full load; all outputs driven all diff pairs driven all differential pairs tri-stated VDD = 3.3 V 14.31818 7 5 6 5 1.8 30 33 300 5 5 5.5 0.4 4 1000 300 MIN 2 VSS - 0.3 -5 -5 -200 0.7 VSS - 0.3 VDD + 0.3 0.35 350 400 70 12 TYP MAX VDD + 0.3 0.8 5 UNITS V V uA uA uA V V mA mA mA mA MHz nH pF pF pF ms kHz us ns ns V V mA ns ns Notes 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1
@ IPULLUP Low-level Output Voltage VOL Current sinking at IPULLUP VOL = 0.4 V (Max VIL - 0.15) to SCLK/SDATA TRI2C (Min VIH + 0.15) Clock/Data Rise Time (Min VIH + 0.15) to SCLK/SDATA TFI2C (Max VIL - 0.15) Clock/Data Fall Time *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%
1 2
Guaranteed by design and characterization, not 100% tested in production. Input frequency should be measured at the REF pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
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ICS950410
Advance Information
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle to cycle
1 3
SYMBOL RDSP VOH VOL IOH IOL tslewr/f tr tf dt1 tskew tjcyc-cyc
CONDITIONS* VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN 12 2.4
TYP
MAX 55 0.55
UNITS V V mA mA mA mA V/ns ns ns % ps ps
NOTES 1 1 1 1 1 1 1 1 1 1 1 1 1
-33 -33 30 38 1 0.5 0.5 45 4 2 2 55 250 500
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (unless otherwise specified) Guaranteed by design and characterization, not 100% tested in production. Spread Spectrum is off
Electrical Characteristics - 48MHz/USB48MHz/24_48MHz
PARAMETER Long Accuracy Clock period Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Edge Rate Rise Time Fall Time Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle to cycle
1
SYMBOL ppm Tperiod RDSP VOH VOL IOH IOL tslewr/f tslewr/f_USB tr tf tr_USB tf_USB dt1 tskew tjcyc-cyc
CONDITIONS* see Tperiod min-max values 48.00MHz output nominal VO = VDD*(0.5) IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate USB48 Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN -100 20.8313 12 2.4
TYP
MAX 100 20.8354 55 0.55
UNITS ppm ns V V mA mA mA mA V/ns V/ns ns ns ns ns % ps ps
NOTES 1,2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
-33 -33 30 38 1 1 0.5 0.5 1 1 45 4 2 2 2 2 2 55 250 500
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not 100% tested in production.
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ICS950410
Advance Information
Electrical Characteristics - CPUCLKK8T/C K8 3.3V Push Pull Differential Pair
PARAMETER Rising Edge Rate Falling Edge Rate Differential Voltage Change in VDIFF_DC Magnitude Common Mode Voltage Change in Common Mode Voltage Jitter, Cycle to cycle Jitter, Accumulated Duty Cycle SYMBOL V/t V/t VDIFF VDIFF VCM VCM tjcyc-cyc tja dt3 Measurement from differential wavefrom Average value during switching transition. Used for determining series termination value. Measurement from differential wavefrom At CPU's test load. (singleended measurement) CONDITIONS* At CPU's test load. 0 V +/- 400 mV (diffential measurment) MIN 2 2 0.4 -150 1.05 -200 0 -1000 45 TYP MAX 10 10 2.3 150 1.45 200 200 1000 55 % UNITS V/ns V/ns V mV V mV ps NOTES 1 1 1 1 1 1 1 1,2,3 1
Output Impedance
RON
15
55
1
Measurement from differential wavefrom *TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% Group Skew tskew
1 2 3
250
ps
1
Guaranteed by design and characterization, not 100% tested in production. All accumulated jitter specifications are guaranteed assuming that REF is at 14.31818MHz Spread Spectrum is off
Electrical Characteristics - HTTCLK
PARAMETER Output Impedance Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Duty Cycle Group Skew Jitter, Cycle-to-cycle
1
SYMBOL ZO VOH1 VOL1 IOH1 IOL1 tslewr/f tr tf dt1 tskew tjcyc-cyc2B
CONDITIONS* VO = VX IOH = -1 mA IOL = 1 mA VOH = 2.0 V VOL = 0.8 V Rise/Fall edge rate between 20% 60% VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 50% VT = 1.5 V VT = 1.5 V
MIN 12 2.4
TYP
MAX 55 0.4 -15
UNITS V V mA mA
NOTES 1 1 1 1 1 1 1 1 1 1 1
10 1 0.5 0.5 45 4 2 2 55 150 250
V/ns ns ns % ps ps
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5% Guaranteed by design and characterization, not 100% tested in production.
0888--04/06/04
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ICS950410
Advance Information
Electrical Characteristics - REF-14.318MHz
PARAMETER Long Accuracy Clock period Output High Voltage Output Low Voltage Output High Current Output Low Current Edge Rate Rise Time Fall Time Skew Duty Cycle Jitter
1 2
SYMBOL ppm Tperiod VOH VOL IOH IOL tslewr/f tr1 tf1 tsk1 dt1 tjcyc-cyc
CONDITIONS see Tperiod min-max values 14.318MHz output nominal IOH = -1 mA IOL = 1 mA VOH @MIN = 1.0 V, VOH@MAX = 3.135 V VOL @MIN = 1.95 V, VOL @MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V VT = 1.5 V VT = 1.5 V
MIN -300 69.8270 2.4
TYP
MAX 300 69.8550 0.4
UNITS ppm ns V V mA mA V/ns ns ns ps % ps
Notes 1,2 2 1 1 1 1 1 1 1 1 1 1
-29 29 1 1 1 45
-23 27 4 2 2 500 55 1000
*TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7 (Rs is used in USB48MHz test only) Guaranteed by design and characterization, not 100% tested in production. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
0888--04/06/04
13
ICS950410
Advance Information
Shared Pin Operation Input/Output Pins
The I/O pins designated by (input/output) on the ICS950410 serve as dual signal functions to the device. During initial power-up, they act as input pins. The logic level (voltage) that is present on these pins at this time is read and stored into a 5-bit internal data latch. At the end of PowerOn reset, (see AC characteristics for timing values), the device changes the mode of operations for these pins to an output function. In this mode the pins produce the specified buffered clocks to external loads. To program (load) the internal configuration register for these pins, a resistor is connected to either the VDD (logic 1) power supply or the GND (logic 0) voltage potential. A 10 Kilohm (10K) resistor is used to provide both the solid CMOS programming voltage needed during the power-up programming period and to provide an insignificant load on the output clock during the subsequent operating period. Figure 1 shows a means of implementing this function when a switch or 2 pin header is used. With no jumper is installed the pin will be pulled high. With the jumper in place the pin will be pulled low. If programmability is not necessary, than only a single resistor is necessary. The programming resistors should be located close to the series termination resistor to minimize the current loop area. It is more important to locate the series termination resistor close to the driver than the programming resistor.
Programming Header Via to Gnd Device Pad 2K W
Via to VDD
8.2K W Clock trace to load Series Term. Res.
Fig. 1
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ICS950410
Advance Information
N
c
L
SYMBOL A A1 b c D E E1 e h L N
INDEX AREA
E1
E
12 D h x 45
a
A A1
In Millimeters COMMON DIMENSIONS MIN MAX 2.41 2.80 0.20 0.40 0.20 0.34 0.13 0.25 SEE VARIATIONS 10.03 10.68 7.40 7.60 0.635 BASIC 0.38 0.64 0.50 1.02 SEE VARIATIONS 0 8 VARIATIONS D mm. MIN MAX 15.75 16.00
In Inches COMMON DIMENSIONS MIN MAX .095 .110 .008 .016 .008 .0135 .005 .010 SEE VARIATIONS .395 .420 .291 .299 0.025 BASIC .015 .025 .020 .040 SEE VARIATIONS 0 8
-Ce
b SEATING PLANE .10 (.004) C
N 48
10-0034
D (inch) MIN .620 MAX .630
Reference Doc.: JEDEC Publication 95, MO-118
300 mil SSOP Package
Ordering Information
ICS950410yFLF-T
Example:
ICS XXXX y F LF- T
Designation for tape and reel packaging Lead Free (Optional) Package Type F = SSOP Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
0888--04/06/04
15

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